Marvell’s Industry Analyst Day last week provided a system-level view of how compute, memory, networking, optics, software, and power delivery must be co-designed as AI clusters scale in size, cost, and criticality. The following six new videos now posted to NextGenInfra.io extend that narrative, offering deeper technical insight into the architectural choices shaping hyperscale AI data centers.
Will Chu describes how Marvell’s custom XPU engagements with hyperscalers have expanded beyond processors to include CXL-enabled memory, infrastructure security devices, and custom NICs built on Certis IP. The session explains how these elements are integrated to improve performance efficiency, reduce latency, and give cloud operators tighter control over AI platforms.
Xi Wang introduces Marvell’s RELIANT software suite and the Golden Cable program, focusing on observability and deployment speed in large AI fabrics. By leveraging DSP data from copper cables and optical modules, Marvell enables remote monitoring and link-level insight, while the Golden Cable reference design provides the industry with a free, end-to-end framework combining hardware, software, and validation.
Rishi Chugh and Roy Chua examine how AI training workloads are driving flatter, two-tier data center network architectures. The discussion highlights the need for predictability and reliability, as network failures during GPU-intensive training runs can invalidate months of compute and significantly increase costs.
Radha Nagarajan outlines Marvell’s approach to optical connectivity across three distance regimes: scale-up links under 30 meters for memory disaggregation, scale-out links from 30 to 300 meters based on Ethernet PAM4, and scale-across connections spanning up to 2,000 kilometers using coherent DWDM. The session ties these domains to Marvell’s internal development efforts, its existing coherent optics business, and the Celestial acquisition.
Annie Liao traces Marvell’s PCIe roadmap from Gen 5 through Gen 8, explaining how higher data rates push electrical solutions toward their limits. She details how optical PCIe—both pluggable and co-packaged—will become necessary to support longer reach, higher bandwidth, and improved signal integrity in AI systems.
Matt Kim addresses power delivery constraints in next-generation AI chips, presenting Marvell’s Package Integrated Voltage Regulator (PIVR) technology. By moving voltage regulation into the XPU package, PIVR increases current density by up to 2×, cuts transmission losses by up to 85%, and supports 4 kW-class and higher compute platforms.
