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Intel unveils IPU roadmap with ASIC and FPGA designs

Intel unveiled its IPU roadmap extending through 2026, featuring new FPGA + Intel architecture platforms (code-named Hot Springs Canyon) and the Mount Morgan (MMG) ASIC, as well as next-generation 800GB products. The discussion also a look at Intel’s open-source software foundation, including the infrastructure programmer development kit (IPDK), which builds upon SPDK, DPDK and P4.

In terms of the timeline, Intel’s roadmap includes:

Here are some details on the 200 Gbps and 400 Gbps IPUs:

Mount Evans — the code name for Intel’s first ASIC IPU, architected and developed with Google Cloud

Oak Springs Canyon — the code name for Intel’s 2nd generation FPGA-based IPU platform built with the Intel Xeon D and the Intel Agilex FPGA, the industry’s leading FPGA in power, efficiency, and performance.

Mount Morgan — a next-generation ASIC IPU expected in 2023/2024.

Hot Springs Canyon — a next-generation FPGA-based IPU platform expected in 2023/2024.

https://www.intel.com/content/www/us/en/newsroom/home.html

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