Rambus validated the interoperability of its DDR4 PHY and the Arm CoreLink DMC-620 Dynamic Memory Controller, which is a fast, single-port Coherent Hub Interface (CHI) for transferring data from its CoreLink CMN-600 (Coherent Mesh Network) to the Rambus DDR4 memory PHY. Together, these IP blocks offer speeds of up to 3200 Mbps, the highest performance memory speed available on the market. Both are DFI 4.0 compliant, allowing the PHY and memory controller to interoperate.
“Design teams face complex challenges in scaling the number of computing cores for advanced datacenter SoCs, while minimizing integration and testing time to ensure faster time-to-market,” said Jeff Defilippi, senior product manager, Infrastructure Business Unit, Arm. “Our collaboration with Rambus removes another degree of difficulty in designing purpose-built SoCs, resulting in higher-performing systems built for the most demanding cloud and enterprise workloads.”