Tektronix, in collaboration with Anritsu, introduced a new PCI EXPRESS 5.0 transceiver (Base and CEM) and reference clock solution for pre-compliance testing. The collaboration between Tektronix and Anritsu enables receiver verification, complementing a world-class transmitter and reference clock test suite.
The PCI EXPRESS 5.0 Base Specification boasts bandwidth of 128 GB/s and the upcoming PCI EXPRESS 6.0 specification will push this to 256 GB/s and include multi-level PAM4 signaling.
The PCI EXPRESS 5.0 transceiver and reference clock solution from Tektronix was developed and continues to be aligned with the 5.0 Base specification, 5.0 CEM specification, and 5.0 test specifications.
Key features include:
- PCI EXPRESS 5.0 (32 GT/s) automated Base & CEM transceiver solution running on DPO700000SX series 70 GHz real time oscilloscope and MP1900A Signal Quality Analyzer-R series (BERT) from Anritsu
- New Receiver automation software from Tektronix with highly efficient algorithms for stressed eye calibration at 32 GT/s & 16 GT/s
- State-of-the-art tool support including SigTest Phoenix with highly parallelized processing to reduce overall test time
- Multiple form factors (M.2 & U.2) and Clocking Architectures (CC, SRNS, SRIS)
- Follows real time evolution of the 5.0 Base specification with 32 GT/s uncorrelated jitter and pulse width jitter measurements implemented to optimize A/D range and minimize noise
- Addresses the increasing challenges of 100 MHz reference clock jitter and signal integrity measurements through full integration with the Silicon Labs “PCIe Clock Jitter” tool and Tektronix’s DPOJET tool
- Industry first pre compliance test fixtures for PCIe 5.0 CEM testing
The companies note that the server/storage industry is rapidly transitioning to PCI EXPRESS 5.0 due to new requirements imposed by 400G Ethernet, cloud AI and modeling (co-processors), storage capacity, and NAND-based storage. This rapid progression brings an entirely new problem set for test and measurement traditionally split into Base silicon level validation and CEM compliance testing with the PCI-SIG.
“Electronics designers today demand future-proofing to protect their innovations’ longevity into tomorrow,” says Takeshi Shima, senior vice president at Anritsu corporation. “Providing a solution through Gen6 gives our customers a sense of our commitment to stay with them on the cutting edge of development.”
“As PCIe becomes faster and more complex with the emergence of the Gen5 standard, engineers are faced with new design challenges, shorter time-to-market windows, new standards specifications to understand and apply, and new compliance testing requirements,” says David Bouse, PCI EXPRESS systems engineer at Tektronix. “It is vital to have a comprehensive test equipment and software solution in place prior to workshop certification. Our PCIe 5.0 test and debug solution can easily guide the engineer through compliance testing and debug to ensure their design meets new standards with a high degree of confidence.”