XCENA raised $135 million in Series B funding to expand deployment of its memory-centric computing platform for AI infrastructure. The round brings total funding to $185 million and values the company at $570 million.
The Santa Clara company said the capital will support global customer deployments, go-to-market expansion, and development of its MX1 computational memory product. Atinum Investment and IMM Investment co-led the round, with participation from strategic and financial investors across Asia.
XCENA targets a key constraint in AI infrastructure: the movement of data between processors and memory. Its platform combines pooled DDR5 memory with near-data processing cores and uses the CXL 3.x standard to expand memory capacity beyond traditional CPU limits.
• Series B funding: $135 million / KRW 202 billion
• Total funding: $185 million
• Valuation: $570 million
• Lead investors: Atinum Investment and IMM Investment
• Product focus: MX1 computational memory
• Architecture: pooled DDR5 memory, near-data processing, CXL 3.x
• Target customers: hyperscalers, telcos, research institutions
• Founding team: semiconductor veterans from Samsung and SK Hynix
“AI workloads are exposing the fundamental limitations of traditional computing architectures as larger models, expanding context windows, and increasingly data-intensive inference workloads drive unprecedented memory demands,” said Jin Kim, CEO and cofounder of XCENA.
🌐 Analysis: XCENA’s funding underscores investor interest in memory-side approaches to AI infrastructure, where bandwidth, latency, and data movement increasingly shape system performance. Its CXL-based strategy places the company in a broader ecosystem of startups and incumbents working to reduce the memory bottleneck as AI inference workloads scale.
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XCENA Profile
| Field | Details |
|---|---|
| Company | XCENA |
| Headquarters | Santa Clara, California |
| Market | AI infrastructure, semiconductor, computational memory |
| Core Technology | Memory-centric computing using pooled DDR5 memory and Near-Data Processing (NDP) cores |
| Standard | CXL 3.0 (Type 3 device with Back Invalidation, supporting CXL.io and CXL.mem) |
| Product Platform | MX1 computational memory controller & full-stack software SDK |
| Funding | $135 million Series B ($185 million total raised) |
| Valuation | $570 million |
| Series B Leads | Atinum Investment and IMM Investment |
| Target Workloads |
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Rather than acting as simple passive CXL memory expansion, the MX1 controller integrates proprietary 64-bit RISC-V processing cores directly into the memory architecture. By executing workloads like decompression, filtering, and data reuse on-device, it breaks the standard “memory wall” by reducing host CPU overhead and eliminating massive data movement penalties over the PCIe bus.