Centec Networks, a fabless silicon developer based in Suzhou, China, introduced its second-generation IP/Ethernet switching processor offering 100 Gbps performance and integrating Layer 2 through Layer 4 capabilities and advanced traffic manager and fabric interfaces. The device is aimed at Carrier Ethernet and Packet Transport equipment, including access, edge, and aggregation IP/Ethernet routing switches, Packet Transport Network (PTN) platforms, Optical Line Termination (OLT) systems and Wireless Backhaul Gateways.
Some highlighted features include:
- On-chip Ethernet Operation, Administration and Management (OAM) based on IEEE802.1ag and ITU-T Y.1731;
- <50ms Automatic Protection Switching (APS) based on ITU-T G.8031/8032;
- Synchronous Ethernet and Packet Timing Protocols such as IEEE1588v2, Network Time Protocol (NTPv4)
- MPLS-TP and Provider Backbone Bridge Traffic Engineering (PBB/PBB-TE) technology.
Additionally, patented loopback mechanisms ensure NPU-like packet-processing flexibility, and multiplexing/demultiplexing technology enables the ability to scale to 256 full-service network ports per chip.
Sampling is underway.
http://www.centecnetworks.com
