Cisco Systems collaborated with IBM on the design of the 40 Gbps ASICs for its new Carrier Routing System (Cisco CRS-1). The Cisco Silicon Packet Processor (SPP) features 38 million gates, approximately 185 million transistors and 188 high-performance programmable 32-bit RISC processors executing 47 billion instructions per second (BIPS). The 18.3-millimeter (mm) square chip — along with nine additional ASICs designed by Cisco and built by IBM for the Cisco CRS-1 — is the result of a strategic multi-year semiconductor technology development effort between the two companies. During the past three years, IBM and Cisco engineers worked closely to develop 10 new custom chips, which are being produced in IBM’s state-of-the-art 300mm semiconductor manufacturing facility in East Fishkill, N.Y., and 200mm facility in Burlington, Vt. http://www.ibm.com/chipshttp://www.cisco.com/go/crs
Cisco Collaborates with IBM on CRS ASICs
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