IBM Telum Processor features interconnect to link up to 32 chips
IBM unveiled its upcoming Telum Processor for artificial intelligence applications. A Telum-based system is planned for the first half of 2022.
Telum is IBM’s first processor that contains on-chip acceleration for AI inferencing while a transaction is taking place. The chip contains 8 processor cores with a deep super-scalar out-of-order instruction pipeline, running with more than 5GHz clock frequency, optimized for the demands of heterogenous enterprise class workloads. The completely redesigned cache and chip-interconnection infrastructure provides 32MB cache per core, and can scale to 32 Telum chips. The dual-chip module design contains 22 billion transistors and 19 miles of wire on 17 metal layers.
The chip is developed in Samsung’s 7nm EUV technology node.
IBM said its Telum processor excels in AI-specific workloads, such financial services workloads like fraud detection, loan processing, clearing and settlement of trades, anti-money laundering and risk analysis.
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