SiFive secured $400 million in an oversubscribed Series G funding round to accelerate development of high-performance RISC-V CPU and AI IP targeting data center deployments. The round, led by Atreides Management, included participation from NVIDIA, Apollo Global Management, T. Rowe Price, Point72, Prosperity7 Ventures, and Sutter Hill Ventures. The financing values SiFive at $3.65 billion and positions the company to expand its RISC-V roadmap for hyperscale and AI infrastructure markets.
SiFive is directing the new capital toward advanced R&D across scalar, vector, and matrix compute architectures, along with expanded software enablement for data center environments. The company is building out support across key platforms including CUDA, Red Hat, and Ubuntu, while deepening collaborations with hyperscalers seeking customizable CPU IP. A key focus is integration with emerging heterogeneous architectures, including alignment with NVIDIA’s NVLink Fusion ecosystem, as data center operators look to optimize performance-per-watt and system-level orchestration for agentic AI workloads.
The company argues that CPUs are regaining strategic importance as AI systems evolve toward more distributed, agentic models that require coordination across compute, memory, and networking layers. SiFive positions its RISC-V architecture as an open-standard alternative to proprietary ISAs, enabling hyperscalers and silicon providers to design differentiated compute platforms with tighter power and workload optimization. With more than 500 designs and over 10 billion cores shipped, SiFive aims to extend its footprint from edge and embedded markets into high-performance AI data center infrastructure.
- $400 million Series G funding round; valuation reaches $3.65 billion
- Led by Atreides Management with participation from NVIDIA, Apollo, T. Rowe Price, Point72, Prosperity7 Ventures, and Sutter Hill Ventures
- Focus on high-performance RISC-V CPU IP for hyperscale and AI data centers
- Investment priorities include scalar, vector, and matrix compute, plus AI accelerators and system IP
- Software ecosystem expansion includes CUDA, Red Hat, and Ubuntu support
- Targeting heterogeneous AI systems, including integration with NVLink Fusion
- More than 500 designs and 10 billion RISC-V cores shipped to date
“Hyperscale customers have made it very clear that it is time to accelerate the availability of open standard alternatives for the data center. Their consistent ask is for customizable CPU solutions in IP form, that will enable them to meaningfully differentiate their data center compute solutions,” said Patrick Little, Chairman and CEO of SiFive.
🌐 Analysis: SiFive traces its origins to the creators of the RISC-V architecture at University of California, Berkeley, including founders Krste Asanović and Yunsup Lee. Established in 2015, the company set out to commercialize RISC-V as an open alternative to proprietary ISAs such as x86 and Arm, initially targeting embedded and IoT markets with configurable CPU cores and development platforms. Early milestones included the launch of its Freedom U and E core families, followed by the Performance P-series cores that expanded into higher-performance applications.
Over time, SiFive built a broad IP portfolio spanning scalar CPUs, vector extensions, and specialized accelerators, along with system-level IP such as interconnects and memory subsystems. The company also introduced design platforms like Freedom and Essential, enabling faster SoC development, and supported ecosystem growth through toolchains, Linux enablement, and partnerships. More recent efforts have focused on high-performance compute, including the Intelligence X-series for AI/ML workloads and data center-class cores aimed at competing in server environments traditionally dominated by Intel and Arm ecosystems.
🌐 Analysis: RISC-V represents a fundamentally different approach to processor design compared to proprietary ISAs such as x86 and Arm. Developed at University of California, Berkeley and now governed by RISC-V International, the architecture is open, royalty-free, and modular. This allows companies to implement only the base instruction set and selectively add extensions—such as vector processing, AI acceleration, or security features—without licensing constraints. The result is a highly customizable CPU design model that aligns with hyperscaler demand for workload-specific silicon and tighter integration across compute, memory, and interconnect.
