eSilicon tapes out 7nm Combo PHY for high bandwidth memory
eSilicon announced the tapeout of a 7nm test chip to provide silicon validation of its physical interface (PHY) to support the new JEDEC standard…
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A journal for networking and telecoms
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eSilicon announced the tapeout of a 7nm test chip to provide silicon validation of its physical interface (PHY) to support the new JEDEC standard…
eSilicon announced the tapeout of a 7nm test ASIC that supports 400G gearbox and retimer functionality. Fabrication is expected in September. A gearbox converts…
eSilicon will move all of its ASIC and IP design to Google Cloud Platform (GCP) this calendar year. eSilicon has been running a hybrid…
eSilicon plans to demonstrate the silicon performance of its 7nm 56G long-reach SerDes during ECOC 2018 (Anritsu booth #408). eSilicon will show a periodic…
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