TeraSignal unveiled its TS5802 intelligent redriver at OFC 2026, targeting performance bottlenecks in 200G+ electrical interconnects used in AI scale-up networks. The CMOS-based device integrates advanced analog equalization with CMIS-compliant link training to improve signal integrity, extend reach, and reduce bit error rates in high-speed PAM4 links. Built on the company’s proprietary TSAFE™ analog front-end architecture, the TS5802 combines a low-noise linear amplifier, CTLE, feed-forward equalization (FFE), and a linear output driver into a unified signal path.
The TS5802 also incorporates TeraSignal’s TSLink™ technology, enabling automated link training and real-time monitoring based on the Optical Internetworking Forum CMIS standard. This allows systems to dynamically adapt equalization parameters to varying channel conditions, addressing signal degradation before it impacts system performance. The device is designed for deployment across a range of AI infrastructure components, including switches, NICs, optical modules, and active copper cables, as well as emerging architectures such as near-packaged optics (NPO), co-packaged optics (CPO), and linear pluggable optics (LPO).
In an interview at OFC, Armond Hairapetian emphasized a key market shift: hyperscalers are increasingly prioritizing latency reduction over power efficiency. He noted that traditional retimers introduce latency and quantization errors, which can lead to link instability and “link flapping.” TeraSignal’s analog approach avoids these issues by maintaining a linear signal path end-to-end, conditioning the signal without digital retiming. This positions the TS5802 for use cases ranging from PCIe Gen6/Gen7 to 100G+ Ethernet and future 200G–400G interconnects, where tighter margins and signal integrity challenges demand more adaptive, low-latency solutions.
- TS5802 is an analog CMOS redriver targeting 200G+ electrical interconnects
- TSAFE architecture integrates CTLE, FFE, amplifier, and output driver in one signal path
- TSLink enables CMIS-based link training and real-time telemetry
- Eliminates need for retimers, reducing latency and quantization-induced errors
- Supports PAM4 signaling and next-gen architectures including ACC, NPO, CPO, LPO, LRO
- Designed for AI accelerators, switches, NICs, and optical modules
- Sampling now; production expected in Q3 2026
“By integrating TSAFE and CMIS-based link training into a single CMOS device, we enable system designers to achieve significantly higher link margin, lower bit error rates, and reliable operation at 200G and above,” said Dr. Armond Hairapetian, CEO of TeraSignal.
🌐 Analysis: TeraSignal is positioning itself at the intersection of two major shifts in AI infrastructure: the move toward linear interconnect architectures and the growing sensitivity to latency in scale-up networks. Its approach aligns with broader industry momentum behind LPO and CPO, where eliminating DSP-based retimers can reduce both latency and power. Competitors in this space include analog and mixed-signal PHY providers such as companies developing linear drive optics and low-power interconnect solutions, while larger players like Broadcom and Marvell continue to push DSP-based architectures. The adoption curve will likely hinge on hyperscaler validation and ecosystem alignment with CMIS and emerging MSAs for linear optics.
Q&A with Dr. Armond Hairapetian, CEO of TeraSignal
Q: What problem is TeraSignal addressing in next-generation AI interconnects?
A: As data rates scale beyond 100G and into 200G+ PAM4, signal integrity becomes increasingly difficult to manage. Traditionally, engineers rely on manual tuning of equalization parameters, which is complex and time-consuming. Our approach automates this process using CMIS-based link training, allowing the system to dynamically optimize performance across different channel conditions without manual intervention.
Q: How does your TSLink technology change the deployment model for linear interconnects?
A: TSLink enables true plug-and-play operation. Instead of requiring engineers to manually adjust settings to achieve acceptable bit error rates, the device automatically negotiates with the host and configures internal filters and equalization. This significantly simplifies deployment, especially in environments like active copper cables and near-packaged optics where tuning complexity can become a bottleneck.
Q: You mentioned a shift in hyperscaler priorities. What are you seeing in the market?
A: The biggest shift we’re seeing is that latency has become more critical than power in many AI scale-up networks. Retimers introduce latency, and that’s increasingly unacceptable for certain workloads. As a result, hyperscalers are actively exploring ways to eliminate retimers and move toward linear architectures that preserve signal integrity without adding delay.
Q: How does TeraSignal’s analog approach compare to traditional retimer-based designs?
A: Retimers digitize the signal, which introduces quantization errors and latency. In contrast, our approach keeps the signal in the analog domain end-to-end, conditioning it so that it arrives at the receiver in optimal form. This avoids error propagation and issues like link flapping, while maintaining low latency.
Q: Where do you see the strongest initial adoption for this technology?
A: We see opportunities across a wide range of interfaces—from PCIe starting at 64G and moving toward PCIe Gen7 speeds, to 100G Ethernet and beyond. Any high-speed PAM4 channel with tight margins can benefit. There’s also a significant opportunity inside systems, where retimers are currently used on boards but introduce latency and power overhead.
Q: How does this technology fit into emerging architectures like CPO and NPO?
A: Even in co-packaged or near-packaged optics, you still need to manage signal degradation across the electrical path. As speeds increase, especially toward 400G per lane, optical components often sit further from the ASIC than ideal. That creates a need for high-performance analog conditioning before driving the optical interface, which is exactly where our technology fits.
Q: What is your go-to-market strategy?
A: We work closely with hyperscalers to understand their system-level challenges and design our solutions accordingly. From there, we collaborate with module and system vendors to achieve design wins. Ultimately, hyperscaler requirements drive adoption across the ecosystem.
Q: What is the current status of your product rollout?
A: Our current portfolio, covering data rates from 64G to 100G+, is moving toward production in the second half of 2026. These products are being evaluated now, with the goal of enabling volume deployments and revenue ramp starting in 2027.
