AMD Puts Helios Into Production as AI Reshapes Data Centers

At its Advancing AI 2026 event in San Francisco, AMD confirmed that its Helios rack-scale AI platform is now in full production status with initial shipments scheduled for the end of the third quarter and a broader ramp in the fourth quarter. AMD Chair and CEO Dr. Lisa Su framed the launch around a fundamental change in AI infrastructure demand: inference now consumes more global AI compute than model training. AMD estimates that inference will account for approximately 60% of global AI compute capacity in 2026 as monthly token consumption exceeds 35 quadrillion—nearly 160 times the level two years ago. The company now projects that the AI accelerator market could reach approximately $1.4 trillion by 2030, while the server CPU market expands from roughly $25 billion today to more than $200 billion.

Helios represents AMD’s move from supplying individual processors toward engineering the complete rack as an integrated system. Each rack connects 72 Instinct MI455X GPUs through a UALink-over-Ethernet scale-up fabric and combines them with 6th Gen EPYC “Venice” CPUs, Pensando Salina DPUs, Vulcano 800G AI NICs, liquid cooling and the ROCm software stack. AMD specifies up to 260 TB/s of scale-up bandwidth, 43 TB/s of scale-out bandwidth, 31 TB of HBM4 memory and 2.9 exaFLOPS of FP4 or 1.4 exaFLOPS of FP8 performance per rack. Each MI455X incorporates 320 billion transistors, 12 compute and I/O chiplets, 432 GB of HBM4 and up to 19.6 TB/s of memory bandwidth using TSMC 2nm and 3nm process technologies.

AMD supported the launch with large deployment commitments and on-stage appearances from Anthropic, OpenAI and Meta. OpenAI’s existing agreement covers up to six gigawatts of AMD GPUs, beginning with an initial MI450 deployment in the second half of 2026. Meta has a separate six-gigawatt agreement, also beginning with MI450-based infrastructure during the second half of 2026. Anthropic plans to deploy up to two gigawatts of Helios capacity, with its first gigawatt beginning in the first half of 2027, while AMD has committed to invest up to $5 billion in the AI company. The partners emphasized co-design across CPUs, GPUs, memory, networking, cooling and software rather than treating the accelerator as an isolated component.

AMD also introduced a heterogeneous inference collaboration with Cerebras. The design assigns prompt processing and large-context prefill to Helios while the Cerebras Wafer-Scale Engine handles memory-bandwidth-intensive decode and low-latency token generation. Joint AMD and Cerebras modeling estimates that the combined system could deliver up to five times more tokens per second per watt than a Cerebras-only configuration at a comparable interactivity level. Cerebras plans to offer the architecture through Cerebras Cloud during the second half of 2026.

The 6th Gen EPYC “Venice” portfolio extends AMD’s platform beyond GPU host processing into the CPU-intensive work surrounding agentic AI. AMD presented a 96-core, high-frequency processor for GPU host nodes; a 256-core, 512-thread processor for dense agent sandboxes; and a 128-core processor for enterprise and general-purpose workloads. The Zen 6 family uses TSMC’s 2nm process and is now in production, with major server OEM and cloud rollouts expected during the fourth quarter. AMD argued that tool execution, database access, orchestration and sandboxed code generation will make CPUs an increasingly important part of AI infrastructure.

“In 2026, for the first time, the world is using more AI compute to run models than to train them,” said Su. “We expect that this year roughly 60% of global AI compute capacity will be used for inference.”

🌐 Analysis: The most consequential change in AMD’s strategy is that the company now treats the rack—and increasingly the complete data center—as the unit of AI system design, combining CPUs, GPUs, memory, Ethernet networking, cooling and software. Helios places AMD in direct competition with other integrated rack-scale platforms, where software maturity, deployment reliability and performance across thousands of interconnected accelerators will matter as much as individual chip specifications.