BM introduced what it describes as the world’s first sub-1 nanometer semiconductor technology, unveiling a 0.7 nm (7 angstrom) logic process built around a new three-dimensional “nanostack” transistor architecture. The technology packs nearly 100 billion transistors onto a fingernail-sized chip—almost twice the density of IBM’s 2 nm technology announced in 2021—and aims to extend Moore’s Law well into the angstrom era. IBM projects the technology could deliver up to 50% higher performance or 70% greater energy efficiency than its 2 nm node, supporting increasingly demanding AI, cloud computing, and high-performance computing workloads.
Rather than continuing conventional transistor scaling, IBM’s researchers developed a vertically stacked nanosheet transistor architecture that layers transistors using sequential 3D integration. The design enables independent material optimization for each transistor layer, allowing engineers to tune performance and power characteristics separately. IBM said the architecture has been experimentally validated through ultra-thin dielectric bonding, dual-channel engineering, CMOS integration, and functional CMOS inverter operation, demonstrating that the technology supports practical logic circuits. Separate research presented at the 2026 VLSI Symposium also showed a 40% SRAM scaling improvement using the nanostack approach, potentially increasing on-chip memory density for AI processors.
IBM developed the technology at its Albany NanoTech research facility alongside semiconductor ecosystem partners. The company said the site will soon host a High Numerical Aperture EUV lithography system from ASML to support future angstrom-node development. IBM also cited ongoing collaborations with Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions to develop manufacturing processes for High NA EUV production. Looking ahead, IBM believes nanostack technology could reach commercial manufacturing within approximately five years while providing a roadmap for at least another decade of semiconductor scaling. The announcement follows IBM’s recent plan to establish Anderon as a standalone quantum foundry company focused on U.S.-based quantum wafer manufacturing.
• First announced semiconductor technology at the 0.7 nm (7 angstrom) node.
• Approximately 100 billion transistors integrated on a fingernail-sized chip.
• Nearly 2x transistor density compared to IBM’s 2 nm technology introduced in 2021.
• New “nanostack” transistor architecture vertically stacks nanosheet transistors using sequential 3D integration.
• Independent material optimization possible for each transistor layer.
• Projected performance improvement of up to 50% versus IBM 2 nm technology.
• Projected energy efficiency improvement of up to 70%.
• Experimental validation includes CMOS integration, dielectric bonding, and functional inverter operation.
• IBM reported 40% SRAM scaling improvement using nanostack memory structures.
• Technology targets AI accelerators, cloud infrastructure, HPC, and next-generation computing platforms.
• IBM estimates commercial production could begin within approximately five years.
• Development conducted at IBM’s Albany NanoTech semiconductor research center.
• Future development will leverage ASML High NA EUV lithography.
• Research partners include Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions.
Jay Gambetta, Director of IBM Research and IBM Fellow, said: “With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency. This industry-first innovation continues IBM’s legacy of leading in next-generation technologies and sets the foundation for the next era of computing.”
🌐 Analysis
IBM’s announcement shifts the discussion beyond traditional process node branding toward transistor architecture innovation. As conventional planar scaling becomes increasingly difficult, semiconductor research has increasingly focused on vertical integration, advanced packaging, backside power delivery, complementary FETs (CFETs), and new channel materials. IBM’s nanostack concept combines several of these directions into a single transistor architecture that could extend CMOS scaling into the angstrom era.
Although IBM no longer manufactures leading-edge processors commercially, its semiconductor research has historically influenced the broader foundry ecosystem. IBM previously pioneered nanosheet gate-all-around transistor technology that has since appeared in advanced manufacturing roadmaps. Commercial deployment of this new architecture would ultimately depend on manufacturing partners and the broader semiconductor supply chain, including High NA EUV lithography, advanced materials, and process integration.
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