Cadence says ready for TSMC’s 5nm FinFET
Cadence Design Systems confirmed that its digital, signoff and custom/analog tools have been certified for Design Rule Manual (DRM) and ...
In Focus: Cadence
MaxLinear employs Cadence for 400Gbps PAM4 chip using 16FF
MaxLinear used Cadence timing signoff tools to deliver its MxL935xx Telluride device, the first 400Gbps PAM4 system on chip (SoC) ...
Cadence intros deep neural-network accelerator AI processor IP
Cadence Design Systems introduced its deep neural-network accelerator (DNA) AI processor intellectual property for developers of articial intelligence semiconductors for ...
Cadence Collaborates with Intel on 14nm Tri-gate Design
Cadence Design Systems announced support for Intel’s 14nm Tri-Gate process technology to enable customers of Intel Custom Foundry. Cadence and ...
A private dossier for networking and telecoms