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Home » ST Advances Panel-Level Packaging with New Pilot Line in France

ST Advances Panel-Level Packaging with New Pilot Line in France

September 19, 2025
in Semiconductors
A A

STMicroelectronics (NYSE: STM) announced a major step forward in advanced chip packaging with plans to build a next-generation Panel-Level Packaging (PLP) pilot line at its Tours, France site. This facility, backed by a $60 million investment, will focus on scaling PLP technology to boost manufacturing efficiency and flexibility across ST’s diverse product portfolio. The pilot line is expected to be operational in Q3 2026.

PLP is a highly automated, advanced packaging and test process that uses large rectangular panels instead of traditional circular wafers. This approach allows higher throughput and lower costs, enabling smaller, more powerful, and cost-effective devices. ST’s PLP technology, which integrates Direct Copper Interconnect (DCI), is currently running at very high volumes in Malaysia, processing more than 5 million units per day on 700x700mm panels.

Fabio Gualandris, President of Quality, Manufacturing, and Technology at ST, emphasized the strategic importance of this investment:

“The development of our PLP capabilities in Tours is aimed at advancing this innovative approach to chip packaging and test manufacturing technology. This will enable us to roll out PLP across a wide portfolio of applications, including RF, analog, power, and microcontrollers, while positioning Europe at the forefront of semiconductor manufacturing innovation.”

The Tours initiative will be closely tied to ST’s heterogeneous integration roadmap, enabling System-in-Package (SiP) solutions that combine multiple chips into a single compact module. ST expects strong collaboration with the local R&D ecosystem, including CERTEM, and synergies with its advanced facilities in Malta.

TopicDetails
Traditional Packaging LimitationsWafer-level packaging (WLP) and flip-chip are reaching scalability and cost-effectiveness limits as devices become smaller and more complex.
PLP ConceptProcesses multiple ICs on a large rectangular panel rather than individual circular wafers, boosting throughput and reducing costs.
ST’s PLP ProductionOperating in Malaysia at very high volumes with over 5 million units/day using 700x700mm panels.
Direct Copper Interconnect (DCI)Replaces traditional wire connections with direct copper bonds for superior electrical performance and reliability.
DCI Advantages
  • Lower power losses from reduced resistance and inductance
  • Improved heat dissipation
  • Enables miniaturization and higher power density
  • Enhanced reliability vs. solder bump connections
System-in-Package (SiP)PLP-DCI supports integration of multiple chips into advanced SiP modules for automotive, industrial, and AI-powered devices.
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