Tokyo-based THine Electronics announced a DSP-free optical chipset built around its ZERO EYE SKEW technology, targeting short-reach optical interconnects for PCI Express 6 and 7 in linear pluggable optics (LPO) and co-packaged optics (CPO) form factors. The company said the approach enables up to 2TB/s of PCIe7 bandwidth while cutting power consumption by 73% and reducing latency by 90% compared with DSP-based optical links.
The chipset eliminates the optical DSP for “slow and wide” scale-up AI interconnects, an architecture increasingly discussed for GPU-dense servers. THine plans to sample VCSEL drivers and transimpedance amplifiers (TIAs) for PCIe6 in 2026, followed by PCIe7 samples in 2027. The work received support from Japan’s National Institute of Information and Communications Technology (NICT) grant program.
Alongside the optical chipset, THine introduced a Sideband Aggregator IC (THCS255) designed to consolidate PCIe6/7 sideband GPIO signals by half or more using high-speed serial technology. The company plans to demonstrate the DSP-free optical interconnect and sideband aggregation solution at OFC 2026 in Los Angeles, March 17–19, at West Hall booth 4575.
• DSP-free optical chipset for PCIe6/7 LPO and CPO targeting short-reach AI server links
• Claimed 73% power reduction and 90% latency reduction versus DSP-based optics
• Supports up to 2TB/s PCIe7 bandwidth for scale-up AI architectures
• VCSEL driver and TIA samples planned for PCIe6 in 2026 and PCIe7 in 2027
• Sideband Aggregator IC reduces PCIe GPIO line count by half or more
• OFC 2026 demonstration scheduled in Los Angeles
“The adoption of artificial intelligence is rapidly expanding. Since AI servers are going to be equipped with over 500 GPUs and memories, we are confident that THine’s proprietary ZERO EYE SKEW® technology, eliminating DSPs from optical links in scale-up AI networks, delivers significant value of efficient costs, lower latency, high-density, and lower power,” said Yasuhiro Takada, Chief Strategy Officer of THine Electronics.
🌐 Analysis
THine’s announcement aligns with growing industry interest in DSP-less optical interconnects for short-reach links, particularly as PCIe6 and PCIe7 roadmaps converge with AI server scale-up requirements. Multiple optical and silicon vendors have outlined LPO and CPO approaches to reduce power and latency, while hyperscalers continue to evaluate tradeoffs between electrical reach, optical complexity, and system cost. THine’s focus on “slow and wide” interconnects positions the company alongside broader efforts to tailor optical architectures specifically for GPU-to-GPU and GPU-to-memory fabrics rather than traditional long-haul or datacenter interconnect use cases.
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