TeraSignal introduced its TS5802 intelligent redriver at OFC 2026, targeting next-generation 200G+ copper interconnects used in AI scale-up networks. The CMOS-based device integrates advanced analog equalization with CMIS-based link training to improve signal integrity, extend reach, and increase link margin in high-speed electrical channels that are increasingly constrained by loss, crosstalk, and noise.
The TS5802 is built on TeraSignal’s TSAFE (TeraSignal Analog Front-End) architecture, which consolidates key analog components—including a low-noise amplifier, CTLE, feed-forward equalizer (FFE), and linear output driver—into a single optimized signal path. By combining CTLE and FFE, the device addresses both pre-cursor and post-cursor inter-symbol interference (ISI), enabling more robust PAM4 signaling at 200G, 400G, and higher data rates. The design targets a range of AI infrastructure use cases, including accelerators, switches, NICs, optical modules, and active copper cables.
In parallel, the TS5802 integrates TSLink technology to enable CMIS-based link training and real-time monitoring. This allows the redriver to dynamically adapt to varying channel conditions, automatically tuning equalization parameters and providing telemetry to detect degradation before failures occur. TeraSignal positions this capability as essential for maintaining reliability and performance in increasingly complex AI data center topologies, including emerging architectures such as active copper cables (ACC), near-packaged optics (NPO), co-packaged optics (CPO), linear pluggable optics (LPO), and linear receive optics (LRO).
- TS5802 is a CMOS-based intelligent redriver designed for 200G+ copper interconnects
- Integrates TSAFE analog front-end with amplifier, CTLE, FFE, and linear output driver
- Combines CTLE and FFE to mitigate both pre- and post-cursor ISI
- Supports PAM4 signaling for 200G, 400G, and higher-speed links
- TSLink enables CMIS-based link training and real-time monitoring
- Dynamically adapts equalization to optimize link performance across varying conditions
- Improves link margin, extends reach, and lowers bit error rates
- Targets AI scale-up environments including GPUs, switches, NICs, and optical modules
- Supports ACC, NPO, CPO, LPO, and LRO architectures
- Samples available now, with production planned for Q3 2026
“TS5802 represents a major leap in analog signal conditioning for high-speed linear interconnects. By integrating TSAFE and CMIS-based link training into a single CMOS device, we enable system designers to achieve significantly higher link margin, lower bit error rates, and reliable operation at 200G and above,” said Dr. Armond Hairapetian, CEO of TeraSignal.
🌐 Analysis: The introduction of intelligent redrivers reflects a broader industry shift toward linear drive architectures and reduced DSP complexity in AI scale-up networks. As hyperscalers evaluate LPO, CPO, and copper-based interconnect extensions, solutions like TS5802 highlight how advanced analog techniques and adaptive link training can extend the viability of copper while improving power efficiency and system cost relative to fully retimed or DSP-heavy approaches.
A key implication of TeraSignal’s TSAFE-based line driver approach is the potential to reshape short-reach interconnect design across AI clusters. By integrating linear amplification, CTLE, and FFE with adaptive control, the TS5802 effectively pushes more signal conditioning into the analog domain while maintaining link intelligence through CMIS-based training. This could reduce reliance on power-hungry DSPs in pluggable optics and active cables, enabling lower-latency, lower-power interconnects for scale-up fabrics. In practice, this supports denser GPU clustering, longer copper reach within racks or across adjacent racks, and more flexible architectural tradeoffs between copper and optics—particularly in emerging LPO and NPO designs where minimizing power per bit is critical.
TeraSignal was founded by Dr. Armond Hairapetian, a veteran of high-speed analog and mixed-signal design with prior leadership roles in interconnect and semiconductor companies. The company focuses on intelligent interconnect solutions that combine analog signal processing with adaptive software control, targeting AI infrastructure, optical modules, and high-speed data center connectivity. Its TSAFE architecture reflects a design philosophy centered on tightly integrated analog front ends paired with real-time link optimization, positioning TeraSignal as a specialist in extending performance and efficiency in next-generation linear interconnect ecosystems.
