Credo Technology introduced its newest 112G PAM4 SerDes Intellectual Property (IP) family on TSMC’s N3 and N7/N6 process technologies. The SerDes IP can be used by other silicon companies to develop chips for 800G and 1.6T connectivity
These two new SerDes IPs complement Credo’s available IP in TSMC’s N5 process technology, which also includes the enhanced N4 version of the 5nm node. This comprehensive SerDes IP family supports a wide range of demands including long reach plus (LR+), long reach (LR), medium reach (MR) and very short reach plus (VSR), for applications including AI, machine learning, high performance compute, switching, security, and optical deployments.
Credo’s DSP-based 112G PAM4 SerDes architectures were developed and proven on TSMC’s 12nm process technology. The 12nm technology was then integrated into Credo’s family of 112G per lane connectivity products for both copper and optical applications at 800G and 1.6T port rates. Credo then ported the 12nm, 112G SerDes to more advanced process technology nodes (N7/N6, N5/N4, and N3) – allowing customers to integrate the silicon proven technology into monolithic ASICs and chiplets.
Jeff Twombly, Vice President of Business Development commented, “Credo is committed to delivering industry leading performance combined with outstanding energy efficiency across the newest optimal process technologies and for a wide variety of reaches. By selecting from our broad portfolio of 112G PAM4 IP, our customers can design complex, monolithic chips rapidly and cost effectively for demanding applications.”
