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Home » Marvell looks to TSMC’s 3nm for custom ASICs

Marvell looks to TSMC’s 3nm for custom ASICs

October 5, 2021
in Semiconductors
A A

Marvell will use TSMC’s 3nm process technology to offer custom silicon for cloud data center, 5G carrier, automotive and enterprise markets.

Marvell is first to introduce a silicon platform that leverages 3nm process technology, advanced die-to-die interface IP, and TSMC’s advanced 2.5D Chip-on-Wafer-on-Substrate (CoWoS) packaging technology.

“Marvell is proud to be the lead ve3nm3nmndor to offer a 3nm platform for cloud-optimized solutions,” said Sandeep Bharathi, Executive Vice President, Central Engineering, System-on-Chip Group at Marvell. “Our new advanced node platform places Marvell on the leading edge of technology readiness with early Si validation of critical IPs to enable fast time-to-market.”

Marvell’s new 3nm multi-chip platform includes two complementary advanced die-to-die interfaces. The first is a flexible extra short reach (XSR) interface for connecting multiple die on a package substrate for applications, like co-packaged optics (CPO) for cloud data centers. 

To address the growing needs for cloud-optimized silicon solutions from leading data center operators, Marvell is also developing an ultra-low power and low-latency parallel die-to-die interface with the highest bandwidth density in the industry. Compatible with emerging Open Compute Project (OCP) standards, the new parallel interface enables high-performance chiplet solutions by connecting multiple silicon devices on an interposer. Both interfaces are also available in 5nm to enable multi-node solutions.

The new platform also incorporates TSMC’s advanced CoWoS packaging technology, empowering continued data infrastructure performance scaling. Marvell said its collaboration with TSMC on CoWoS allows customers to build high-performance solutions for “the most demanding cloud data center applications.”

https://www.marvell.com/products/custom-asic.html  

  • Earlier this year, TSMC stated that its 3nm technology (N3) will offer up to 70% logic density gain, up to 15% speed improvement at the same power and up to 30% power reduction at the same speed as compared with N5 technology. N3 is expected to receive multiple customer product tape-outs in 2021. In addition, volume production is targeted in second half of 2022.
Tags: 3nmMarvellSiliconTSMC
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