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Home » NextSilicon Maverick-2 Chips Power Sandia’s Most Unconventional Supercomputer Yet

NextSilicon Maverick-2 Chips Power Sandia’s Most Unconventional Supercomputer Yet

December 8, 2025
in All, Semiconductors
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Sandia National Laboratories has deployed a new class of supercomputer that trades scale for architectural experimentation. Developed with NextSilicon, the Spectra system introduces a nontraditional design that prioritizes adaptive compute over raw FLOPS, aiming to accelerate high-stakes national security simulations central to the U.S. nuclear deterrence mission. The Vanguard-program system arrives with 128 Maverick-2 dual-die accelerators—specialized chips that analyze code and dynamically prioritize instructions, stepping away from the uniform data treatment typical of CPUs and GPUs.

Spectra’s role is to determine whether this architecture can improve the accuracy, speed and power efficiency of complex workloads such as advanced fluid dynamics used to assess stockpile reliability without underground testing. Sandia is coordinating the evaluation with Lawrence Livermore and Los Alamos under NNSA’s Advanced Simulation and Computing program. Early support for HPCG, LAMMPS and SPARTA indicates that Spectra can run mission-relevant codes out of the box, a key requirement for backward compatibility in an environment where software portability often consumes years.

The system’s 64 compute nodes were integrated by Penguin Solutions, which built custom servers supporting up to four high-performance Open Accelerator Modules, providing headroom for Sandia to scale power and performance over time. Paired with Chilldyne’s negative-pressure liquid cooling and Penguin’s Tundra power-and-thermal infrastructure, Spectra is engineered as an expandable testbed for evaluating how adaptive chips might reshape future ASC production systems—advancing efficiency rather than simply increasing system size.

• 128 NextSilicon Maverick-2 dual-die accelerators across 64 compute nodes

• Adaptive architecture prioritizes code paths in real time rather than treating all data equally

• First supercomputer to integrate Maverick-2 chips at scale

• Supports HPCG, LAMMPS, SPARTA on day one with minimal code modification

• Builds on Vanguard program experiments such as Astra (Arm-based, 2018)

• Penguin Solutions integration with Chilldyne liquid cooling for high-density operation

• Designed as an expandable platform supporting up to four Open Accelerator Modules per server

“We have deployed a first-of-its-kind computing capability, and it’s the result of this tremendous partnership between the national labs and industry,” said James Laros, senior scientist and project lead at Sandia National Laboratories.

https://newsreleases.sandia.gov/not-the-largest-supercomputer-but-maybe-the-most-interesting

🌐  Analysis

Spectra signals a growing push toward alternative compute architectures that emphasize adaptive scheduling and power-lean logic rather than brute-force GPU scaling. The project follows earlier Vanguard work validating Arm-based systems and arrives as national labs evaluate heterogeneous pathways—including RISC-V, custom accelerators and AI-driven runtime optimization—to sustain simulation performance amid energy-constrained data centers. NextSilicon’s model aligns with broader industry trends toward domain-specific acceleration, competing conceptually with approaches from Cerebras, SambaNova and Groq, though targeted squarely at ASC-class physics workloads rather than AI inference.

Addendum: NextSilicon’s Maverick-2 and RISC-V Core

In October, NextSilicon provided the most detailed look yet at its Maverick-2 processor architecture, outlining a dataflow-driven design intended to deliver major efficiency gains for AI and HPC workloads. The company said Maverick-2 accelerators can provide up to 10x higher performance than leading GPUs at roughly 60% less power for algorithmically complex tasks, particularly where branching, irregular memory access, or nonuniform parallelism limit traditional architectures. The design centers on NextSilicon’s Intelligent Compute Architecture, which shifts much of the scheduling and control overhead from hardware into software algorithms that adapt execution paths in real time.

A central element of the October announcement was Maverick-2’s ability to run unmodified code across a broad range of domains — including CUDA, Fortran, and legacy simulation software — eliminating the porting cycles, rewrites, and proprietary tooling normally required for new accelerators. Benchmark results released by the company highlighted strengths in graph analytics (10x PageRank throughput), high-throughput updates (32.6 GUPS at 460W), and competitive HPCG performance at about half the power of current GPU platforms. The chip’s HBM3e memory subsystem was validated through STREAM to deliver full bandwidth for data-intensive workloads.

NextSilicon also unveiled Arbel, a new enterprise-grade RISC-V core built on TSMC’s 5nm node. Designed to match x86-class CPUs on performance and power efficiency, Arbel represents a second architectural path for the company — one aimed at general-purpose compute and datacenter integration. NextSilicon positioned this as part of a broader strategy to offer both vertically integrated accelerator solutions and licensable silicon IP that could support a growing RISC-V ecosystem.

🌐 We’re tracking the latest developments in AI infrastructure. Follow our ongoing coverage at: https://convergedigest.com/category/ai-infrastructure/

🌐 We’re launching the “Data Center Networking for AI” series on NextGenInfra.io and inviting companies building real solutions—silicon, optics, fabrics, switches, software, orchestration—to share their views on video and in our expert report. To get involved, send a note to [email protected] or [email protected].

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