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Home » #OCP: Compressed Dev Cycles for AI Interconnects

#OCP: Compressed Dev Cycles for AI Interconnects

October 16, 2024
in Semiconductors
A A

How is the industry adapting to compressed demand cycles in high-speed I/O?

Hani Daou, Business Development Manager from Multilane explains:

– Demand cycles are compressing between 112G, 224G, and 448G technologies, creating potential interoperability challenges
– The industry needs to adopt a 100% testing mindset to address interconnect and SerDes failures
– Multilane is developing new equipment for high lane count testing with 100% coverage for backplanes, transceivers, and passive interconnects

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Tags: 224GMultilaneOCP24Test
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Jim Carroll

Jim Carroll

Editor and Publisher, Converge! Network Digest, Optical Networks Daily - Covering the full stack of network convergence from Silicon Valley

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