PCIe 8.0 Advances Toward 256 GT/s and 1 TB/s by 2028

PCI-SIG advances the PCIe 8.0 specification toward a targeted 2028 release with draft 0.5 now available to members, keeping the interconnect roadmap on pace for 256.0 GT/s signaling and up to 1.0 TB/s of bi-directional bandwidth in a x16 configuration. The organization said the latest draft arrived ahead of the normal schedule and incorporates member feedback gathered after draft 0.3 debuted in September 2025.

The PCIe 8.0 specification targets the next generation of AI clusters, hyperscale data centers, high-speed networking, edge systems, and quantum computing platforms that continue to push requirements for bandwidth density and low-latency communication. PCI-SIG plans to double throughput again over PCIe 7.0 while maintaining backwards compatibility with prior generations of PCIe technology. The work also focuses on achieving latency, forward error correction (FEC), and reliability goals as signaling rates continue to climb.

PCI-SIG said the PCIe 8.0 effort includes evaluation of new connector technologies, additional protocol enhancements to improve bandwidth efficiency, and new techniques to reduce power consumption. The organization now counts more than 1,000 member companies participating in specification development across the ecosystem spanning CPUs, GPUs, AI accelerators, switches, NICs, storage systems, and test equipment vendors.

• PCIe 8.0 targets 256.0 GT/s raw transfer speeds
• Up to 1.0 TB/s bi-directional bandwidth in x16 configuration
• Draft 0.5 now available to PCI-SIG members
• Full PCIe 8.0 specification release remains targeted for 2028
• Focus areas include AI, data centers, networking, edge, and quantum computing
• Objectives include backwards compatibility, lower power, and improved protocol efficiency
• PCI-SIG is evaluating new connector technologies for future implementations

“PCIe technology continues to evolve to meet the growing bandwidth demands of the industry’s most data-intensive applications,” said Al Yanes, President and Chairperson of PCI-SIG. “With draft 0.5 now available, we are pleased to see the PCIe 8.0 specification progressing ahead of the typical development schedule.”

🌐 Analysis: PCIe signaling rates continue to accelerate in response to AI infrastructure scaling pressures, especially as GPU clusters and disaggregated memory architectures demand higher bandwidth between accelerators, CPUs, storage, and networking fabrics. PCIe 7.0, finalized in 2025 at 128 GT/s, already pushed PAM4 signaling into mainstream interconnect design, and PCIe 8.0 will likely intensify industry adoption of advanced retimers, co-packaged optics, linear pluggable optics, and new connector ecosystems to maintain signal integrity across large AI systems.

🌐 The PCIe roadmap also intersects directly with emerging scale-up AI architectures from NVIDIA, AMD, Broadcom, Astera Labs, and hyperscale cloud operators. As AI factories expand toward rack-scale and row-scale accelerator deployments, PCIe increasingly serves as a foundational transport layer alongside Ethernet, Ultra Accelerator Link (UALink), NVLink, and custom fabric technologies. The move to 256 GT/s also raises new thermal and power delivery challenges across boards, cables, and backplanes, reinforcing industry momentum toward optical interconnects deeper inside the server and rack.