Cadence introduced a new agentic AI workflow aimed at automating front-end silicon design and verification with the launch of its ChipStack AI Super Agent. The company positions the software as an autonomous “silicon agent” that generates RTL, builds and executes testbenches, creates test plans, orchestrates regression testing, debugs issues, and applies fixes directly from specifications and high-level design descriptions. Cadence says the system can deliver up to 10X productivity improvements across coding and verification tasks.
The ChipStack AI Super Agent integrates with Cadence’s existing EDA portfolio, including the Verisium Verification Platform, Cerebrus Intelligent Chip Explorer, and the JedAI data and AI platform. The workflow coordinates multiple AI agents that call underlying Cadence tools to execute tasks across the front-end design flow. It supports both cloud-based and on-premises AI models, including NVIDIA Nemotron models customized with NeMo as well as hosted large language models such as OpenAI GPT. Cadence says its broader AI-driven tools have already supported more than 1,000 production tapeouts.
Early deployments are underway with Altera, NVIDIA, Qualcomm, and Tenstorrent. Customers report verification acceleration ranging from 4X to 10X in selected projects, including reductions in formal verification time and faster regression closure. Cadence says the product is available now in early access, with broader rollouts expected as customers expand usage across additional design teams.
• Automates RTL coding, testbench generation, test plan creation, regression orchestration, debugging, and issue resolution
• Integrates with Verisium, Cerebrus, and JedAI platforms
• Supports cloud and on-prem inference, including NVIDIA Nemotron and OpenAI GPT models
• Early deployments at Altera, NVIDIA, Qualcomm, and Tenstorrent
• Claimed productivity gains: up to 10X in coding and verification workflows
• Available in early access
“By leveraging intelligent agents that autonomously call our underlying tools, we are enabling dramatic productivity gains for our customers in critical design and verification tasks while freeing scarce engineering talent to focus on innovation,” said Anirudh Devgan, president and CEO, Cadence.
🌐 Analysis: Cadence is extending AI deeper into core EDA workflows at a time when chip complexity and AI-driven silicon programs are straining engineering resources. The move also positions Cadence competitively against Synopsys and Siemens EDA, both of which are expanding generative and agentic AI capabilities across design and verification flows, as AI-native silicon programs accelerate across hyperscale, automotive, and RISC-V ecosystems.
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