The CXL Consortium announced the release of the Compute Express Link (CXL) 3.1 specification with improved fabric manageability to take CXL beyond the rack and enable disaggregated systems.
Highlights of the CXL 3.1 specification:
CXL Fabric improvements and extensions
Fabric Decode/Routing requirements Fabric Manager API definition for PBR (Port Based Routing) Switch Host-to-host communication with Global Integrated Memory (GIM) concept Direct P2P CXL.mem support through PBR Switches
Extended Meta Data with support for up to 32-bits per cache line of host specific state Improved visibility into CXL memory device errors Expanded visibility and control over CXL memory device RAS (Reliability, Availability, Serviceability)
Full backward compatibility with CXL 2.0, CXL 1.1, and CXL 1.0