Synopsys highlighted its role in the development of AMD’s new Instinct MI455X GPU at AMD Advancing AI 2026, saying AMD relied on the Synopsys 3DIC Compiler platform to accelerate the design of the multi-die AI accelerator. The collaboration centered on advanced package co-design, automated die-to-die and die-to-package routing, integrated multiphysics analysis, verification, and emulation technologies that supported development of AMD’s latest AI accelerator.
AMD used Synopsys’ 3DIC Compiler as a unified exploration-to-signoff platform for heterogeneous integration, floorplanning, partitioning, routing, and package optimization. According to Synopsys, the integrated workflow reduced manual design effort while addressing increasingly complex thermal, power delivery, and electromagnetic challenges associated with large multi-die AI processors. AMD also incorporated Synopsys memory interface IP to support the high-bandwidth data movement requirements of the MI455X platform.
Beyond physical implementation, AMD employed Synopsys ZeBu emulation systems for early software development and system validation prior to silicon availability. ZeBu supported software stack validation, save-and-restore debugging, and execution of high-fidelity workload models reaching up to 20 billion gates. AMD also utilized Synopsys VC Formal, VCS RTL simulation, and VC LP verification technologies to improve verification coverage and validate functionality across both die-level and SoC-level environments. Separately, Synopsys noted that Microsoft’s recently announced Azure HXv2 platform, powered by 6th Gen AMD EPYC processors, expands cloud infrastructure available for Synopsys AI-driven EDA workloads.
• AMD used Synopsys 3DIC Compiler for multi-die exploration, implementation, and signoff.
• Platform integrates automated die-to-die and die-to-package routing.
• Integrated multiphysics analysis addresses thermal, power, and electromagnetic effects.
• Synopsys memory interface IP supports MI455X memory subsystem implementation.
• ZeBu emulation enabled early software development before first silicon.
• Emulation models scaled to as many as 20 billion gates.
• AMD also deployed VC Formal, VCS RTL simulation, and VC LP verification tools.
• Microsoft Azure HXv2 expands cloud infrastructure optimized for Synopsys EDA workloads.
“In this era of unprecedented AI infrastructure buildout, engineering teams need solutions enabling extreme co-design to accelerate innovation cycles and deliver leading-edge performance with first-time right silicon,” said Shankar Krishnamoorthy, chief product development officer at Synopsys.
🌐 Analysis
The announcement illustrates how AI accelerator development increasingly depends on tightly integrated electronic design automation (EDA), advanced packaging, verification, and emulation technologies rather than traditional chip implementation alone. Multi-die architectures require concurrent optimization across silicon, package, memory, thermal behavior, and software readiness, making unified design environments increasingly important for accelerating development schedules.
Synopsys continues to position its EDA portfolio around the AI infrastructure buildout by integrating physical design, advanced packaging, verification, emulation, and AI-assisted automation. AMD’s MI455X program joins a growing list of hyperscale AI platforms adopting complex chiplet-based architectures that require comprehensive co-design workflows extending from architecture through silicon validation.
