Synopsys expanded its collaboration with TSMC across advanced-node EDA flows, silicon-proven IP, 3D multi-die design, and co-packaged optics enablement for next-generation AI and high-performance computing systems.
The work spans TSMC’s 3nm and 2nm process families, A16 with Super Power Rail, and A14, along with 3DFabric technologies including TSMC-SoIC and CoWoS. Synopsys said its 3DIC Compiler now supports TSMC CoWoS technology at 5.5x reticle interposer sizes, while integrations with RedHawk-SC, RedHawk-SC Electrothermal, Totem, PathFinder-SC, and Ansys HFSS extend multiphysics signoff across power, thermal, electromagnetic, and signal-integrity domains.
The companies also are collaborating on agentic run assistance in Synopsys Fusion Compiler for TSMC A14 using the NanoFlex Pro architecture. Synopsys said the work identifies timing-improvement opportunities across design-flow stages to improve PPA and productivity. Additional AI-assisted physical verification work in Synopsys IC Validator aims to speed DRC issue identification and resolution.
- Synopsys achieved silicon bring-up of low-power M-PHY v6.0 IP on TSMC N2P.
- The company taped out 64G UCIe IP and advanced 224G IP for AI system connectivity.
- IP milestones span PCIe 7.0, HBM4, DDR5 MRDIMM Gen2, LPDDR6/5X/5, UCIe 64G, and M-PHY v6.0 across TSMC N5, N3P, and N2P.
- Synopsys expanded Foundation IP for TSMC N3P and N2P, including embedded memories, logic libraries, and IOs.
- Multiphysics enablement for COUPE combines optical, photonic, electromagnetic, and electrothermal simulation to support co-packaged optics.
- Synopsys also launched a UCIe IP ASIL B solution on TSMC N5A for automotive chiplet designs.
“TSMC’s most advanced process and packaging technologies are opening new frontiers for performance, bandwidth, and energy efficiency in AI and autonomous systems,” said Michael Buehler-Garcia, Senior Vice President at Synopsys. “Through our deep collaboration, Synopsys is delivering AI-driven design flows, advanced multiphysics signoff, and a comprehensive portfolio of proven interface and foundation IP that help customers accelerate innovation and achieve outstanding quality of results.”
🌐 Analysis: The announcement highlights how AI accelerator design now depends on a full stack that extends beyond transistor scaling into packaging, IP reuse, multiphysics signoff, and optical-electrical integration. TSMC’s A14, A16, N2P, CoWoS, SoIC, and COUPE roadmaps create a broader design surface for EDA vendors, while Synopsys is positioning its flow around the bottlenecks that matter most for AI systems: power integrity, thermal behavior, chiplet connectivity, and high-speed optical I/O.
