At this week’s Hot Chips event at Stanford University, Intel presented two sessions revealing technical specifications and features of the Xeon platform architecture and offerings coming in 2024, along with additional information on its forthcoming 5th Gen Intel Xeon® processors launching later this year. A separate session outlined new capabilities related to its Intel Agilex 9 Direct RF-Series FPGAs.
The new Intel Xeon platform utilizes modular system-on-chips (SoCs) for increased scalability and flexibility to deliver a range of products that meet the growing scale, processing and power efficiency needs for AI, cloud and enterprise installations.
- P-core and E-core are delivered with shared intellectual property (IP), firmware and OS software stack.
- Fastest DDR and new high-bandwidth multiplexed combined rank (MCR) DIMMs.
- New Intel Flat Memory enables hardware-managed data movement between DDR5 and CXL memory, making total capacity visible to software.
- CXL 2.0 support for all device types with backward compatibility to CXL 1.1.
- Advanced I/O with up to 136 lanes PCIe 5.0/CXL 2.0 and up to six UPI links.
Intel Xeon processors with E-cores (Sierra Forest) are enhanced to deliver density-optimized compute in the most power-efficient manner. Xeon processors with E-cores provide best-in-class power-performance density, offering distinct advantages for cloud-native and hyperscale workloads.
- 2.5x better rack density and 2.4x higher performance per watt1.
- Support for 1S and 2S servers, with up to 144c per CPU and TDP as low as 200W.
- Modern instruction set with robust security, virtualization and AVX with AI extensions.
- Foundational memory RAS features such as machine check, data cache ECC standard in all Xeon CPUs.
Intel Xeon processors with P-cores (Granite Rapids) are optimized to deliver the lowest total cost of ownership (TCO) for high-core performance-sensitive workloads and general-purpose compute workloads. Today, Xeon enables better AI performance than any other CPU2, and Granite Rapids will further enhance AI performance. Built-in accelerators give an additional boost to targeted workloads for even greater performance and efficiency.
- 2-3x better performance for mixed AI workloads3.
- Enhanced Intel AMX with support for new FP16 instructions.
- Higher memory bandwidth, core count, cache for compute intensive workloads.
- Socket scalability from one socket to eight sockets.
Intel Agilex 9 Direct RF-Series FPGAs with Integrated 64 Gsps (giga-samples per second) Data Converters and a new wideband agility reference design include both wideband and narrowband receivers within the same multichip package. The wideband receiver provides an unprecedented 32 GHz of RF bandwidth to the FPG