Marvell introduced its Teralynx T100, a 102.4 Tbps Ethernet switch silicon platform aimed squarely at the rapidly growing AI infrastructure market. The company says the device is the industry’s first switch at this bandwidth tier designed specifically for AI and cloud-scale data center networks, with sampling to customers beginning this quarter.
Built on a 3nm process, the Teralynx T100 targets one of the biggest constraints facing AI cluster operators: power efficiency. Marvell says the chip consumes under 1,000 watts typical power—up to 25% lower than competing devices—at a time when GPU and XPU racks are nearing 120 kW of power draw. With networking components accounting for roughly 15–25% of total rack power, Marvell is positioning lower-power switching silicon as a way for operators to deploy more accelerators within existing facility power limits without expanding electrical infrastructure.
The Teralynx T100 is designed for both scale-out and scale-up AI fabrics. Marvell says it supports up to 512 ports of radix for large-scale Ethernet AI clusters and can also accommodate emerging scale-up fabric protocols, including Ethernet Scale-Up Networking (ESUN) and Ultra Ethernet Consortium requirements. The device will be offered in multiple packaging options including standard BGA, co-packaged copper, and co-packaged optics, giving hyperscalers flexibility as optical interconnect strategies continue to evolve inside next-generation AI clusters.
- 102.4 Tbps Ethernet switch silicon optimized for AI and cloud infrastructure
- Under 1,000W typical power consumption
- Up to 25% lower power than competitive platforms, according to Marvell
- Built on advanced 3nm process technology
- Supports up to 512-port radix for scale-out AI fabrics
- Supports ESUN, Ultra Ethernet Consortium specifications, and evolving AI Ethernet fabrics
- Available in BGA, co-packaged copper, and co-packaged optics implementations
- Includes SDK, OCP SAI support, and SONiC compatibility
- Sampling begins this quarter
“The Teralynx T100 was purpose-built for AI—designed without the legacy baggage that inflates power, and engineered to deliver the deterministic performance and efficiency required to scale next-generation data center infrastructure,” said Rishi Chugh, vice president and general manager of Marvell’s Data Center Switch Business Unit.
🌐 Analysis
Marvell’s Teralynx T100 arrives as the market for AI networking silicon enters a new phase defined by power constraints, cluster scale, and architectural specialization. While previous generations of Ethernet switch silicon evolved from enterprise and cloud networking requirements, the T100 reflects a shift toward chips tuned specifically for AI training and inference fabrics, where latency, congestion management, and power efficiency directly influence GPU utilization. The 102.4 Tbps class is becoming the new battleground for next-generation AI cluster interconnects.
The launch also expands Marvell’s broader AI infrastructure portfolio, which now spans switching silicon, optical DSPs, custom ASICs, co-packaged optics, and interconnect technologies. Competition remains intense across the AI networking stack, with Broadcom, NVIDIA, Cisco, and several emerging Ethernet ecosystem players all pushing high-bandwidth, lower-power fabric architectures for clusters scaling to tens or hundreds of thousands of accelerators.
